1. Field of the Invention
The present invention relates to a semiconductor apparatus and a method of manufacturing a semiconductor apparatus and, particularly, to a semiconductor apparatus and a method of manufacturing a semiconductor apparatus with a power MOSFET structure.
2. Description of Related Art
Recently, in a vertical power metal oxide semiconductor field effect transistor (MOSFET), a superjunction structure is used for lower on-resistance and higher withstand voltage. A vertical power MOSFET with a superjunction structure is described in Japanese Unexamined Patent Application Publication No. 2006-93430 (Ninomiya).
FIGS. 7A and 7B show the technique which is described in Ninomiya. FIG. 7A shows the sectional structure of a power MOSFET 70 along the line 7A-7A, and FIG. 7B shows the layout on the upper surface of the power MOSFET 70. The power MOSFET 70 has a superjunction structure in which a column region 73 is formed in a drift region 72 which is formed on a semiconductor substrate 71. As shown in the upper-surface layout of FIG. 7B, the column regions 73 are equally spaced from each other in the power MOSFET 70. Above the semiconductor substrate 71, a trench (groove) which is deeper than a base region 74 and a source region 75 that are vertically disposed on the drift region 72 is formed. The drift region 72 and the semiconductor substrate 71 serve as a drain region. The trench is filled with a gate electrode 76 (i.e. a trench gate structure). If a bias voltage is applied between the gate electrode 76 and a source electrode 77 of the power MOSFET 70, a channel is formed in the base region 74 in the vicinity of the gate electrode 76. As a result, charges move between the source region 75 and a drain region through the channel, thereby entering the on-state.
As described above, the column regions 73 are equally spaced from each other in the power MOSFET which is described in Ninomiya. Therefore, charge imbalance does not occur. It is thereby possible to achieve a high withstand voltage by the superjunction structure.
Japanese Unexamined Patent Application Publication No. 2006-165441 (Ninomiya et al.) discloses a power MOSFET in which a column region in a device active area and a column region in a peripheral area have the same depth to thereby equalize the charge balance between the device active area and the peripheral area (cf. FIGS. 8A and 8B). In the power MOSFET 80, a depletion layer is generated uniformly in the device active area and the peripheral area, so that a depletion layer is uniformly thick. This improves the breakdown voltage of a device, thereby heightening a withstand voltage.
However, in the technique described in Ninomiya, the distance between the column region and the gate electrode is not uniform, which results in an increase in on-resistance. FIG. 9 shows the column region which can be considered based on FIG. 7B. The column region of the related art is circular. Thus, the distance between the column region and the gate electrode is not uniform, and accordingly the thickness of a channel is not uniform. Specifically, a current path is narrow in the part where the column region and the gate electrode is closest, and resistance is high in such a part. FIG. 10 shows a current path which can be considered based on Ninomiya. This causes an increase in on-resistance.